发明名称 System and method for intersample timing error reduction
摘要 A system clock for a system for measuring at least one given quantity having a value which does not vary significantly from a given frequency, the system clock comprises a controller for sampling said given quantity at a rate determined by an oscillator frequency, and a programmable oscillator for generating the oscillator frequency, said programmable oscillator being programmable to produce said oscillator frequency at a frequency which is substantially identical to a high order harmonic of said given frequency of the quantity to be measured.
申请公布号 US6614216(B2) 申请公布日期 2003.09.02
申请号 US20010778588 申请日期 2001.02.07
申请人 SQUARE D COMPANY 发明人 LONG AVERY D.
分类号 G01R31/319;(IPC1-7):G01R23/02;G01R13/14 主分类号 G01R31/319
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