发明名称 |
Semiconductor memory device |
摘要 |
A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.
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申请公布号 |
US6614712(B2) |
申请公布日期 |
2003.09.02 |
申请号 |
US20020329669 |
申请日期 |
2002.12.27 |
申请人 |
FUJITSU LIMITED |
发明人 |
UCHIDA TOSHIYA;HARA KOTA;FUJIOKA SHINYA |
分类号 |
G11C11/401;G11C5/06;G11C8/08;G11C11/409;G11C11/4091;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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