发明名称 Logic architecture for single event upset immunity
摘要 An SEU immune logic architecture includes a dual path logic gate coupled to a dual to single path converter. A first and a second logic element within the dual path logic gate are functionally and possibly structurally equivalent, and are coupled to receive input signals spanning redundant input signal sets. A given logic structure within the first logic element may receive specified input signals within a particular input signal set, while an analogous logic structure within the second logic element may receive corresponding input signals within the counterpart input signal set. A radiation induced transient pulse that affects one input signal may affect an output signal asserted by one logic structure; however, since the transient pulse doesn't affect a corresponding input signal applied to the analogous logic structure, the dual path logic gate may output at least one correctly valued signal when a transient pulse occurs. The dual to single path converter is coupled to receive signals output by the dual path logic gate. In the event that a transient signal appears at an input of the dual to single path converter, a current path may be interrupted, and a correct output signal value is maintained as a result of stray capacitance present at an output node.
申请公布号 US6614257(B2) 申请公布日期 2003.09.02
申请号 US20010854247 申请日期 2001.05.11
申请人 BAE SYSTEMS INFORMATION AND ELECTRONICS SYSTEMS INTEGRATION, INC. 发明人 KNOWLES KENNETH R.
分类号 H03K19/003;H03K19/007;(IPC1-7):H03K19/003 主分类号 H03K19/003
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