Current controlled multi-state parallel test for semiconductor device

摘要

A semiconductor memory device (300) having a parallel test circuit is disclosed. A test data path (308) receives parallel I/O line (I/O0-I/O7) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit (312). The gate control circuit (312) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver (314) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit (312), the open drain output driver (314) drives a data output (DQ) to a first, second or intermediate logic level.