| 摘要 |
A method of fabricating a system on a chip device. On a substrate having a memory cell region and a peripheral circuit region a gate oxide layer and a polysilicon layer are formed. The peripheral circuit region can further be divided into a logic device region and a hybrid circuit region. A dielectric layer is formed on the peripheral circuit region. A cap layer and a conductive layer are further formed on the polysilicon layer in the memory cell region and on the dielectric layer in the peripheral circuit region. Using the dielectric layer in the peripheral circuit region and the gate oxide layer in the memory cell region as etch stop, the cap layer and the conductive layer in the peripheral circuit region, and the cap layer, the conductive layer and the polysilicon layer are patterned. As a result, at least a gate and a top electrode are formed in the memory cell region and the hybrid circuit region, respectively. Using the gate oxide layer in the peripheral circuit region as an etch stop, the dielectric layer and the conductive layer in the peripheral circuit region are patterned to form a gate in the logic circuit region and the hybrid circuit region, respectively. |
