| 摘要 |
A low power, sigma-delta analog-to-digital converter having an improved reference multiplexer that eliminates noise in a reference voltage signal. The sigma-delta analog-to-digital converter includes a passive filter circuit connected to receive a differential reference voltage input. The improved differential multiplexer couples to the passive filter circuit to receive the reference voltage signal. This differential multiplexer includes three modes of operation: (1) direct coupling of its differential input to its differential output, (2) cross-coupling of its differential input to its differential output, and (3) setting of the differential output to a fixed voltage to discharge the parasitic capacitance associated its differential output every clock cycle. This last mode of operation eliminates the noise of the reference voltage signal and ultimately the sigma-delta ADC. A sigma-delta integrator receives the differential output from the differential multiplexer. A comparator couples to the output of the sigma-delta integrator to provide a decision signal to the differential multiplexer for enabling and disabling the first and second modes of operation; while a clocking signal fed to the differential multiplexer is responsible for enabling and disabling the third mode of operation.
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