| 摘要 |
A semiconductor memory is provided that comprises a plurality of memory cell arrays (ALY), each memory cell array (ALY) including bit lines (BL, /BL) and memory cells each constituted by a variable capacitor, the memory cell arrays (ALY) operating at mutually different timings. The bit lines (BL, /BL) of each memory cell array (ALY) are connected to bit lines (BL, /BL) of the other memory cell arrays (ALY) via connecting wires (CW). Accordingly, the actual capacitances of the bit lines (BL, /BL) are the capacitances of bit lines (BL, /BL) of that memory cell array (ALY) itself plus that of the other memory cell arrays (ALY) plus the capacitances of the connecting wires (CW). Therefore, when data is read from the memory cells, the variations in voltage of the bit lines (BL, /BL) caused by the capacitive division can be enlarged. Consequently, the read margin can be prevented from being degraded, and the manufacturing yield of semiconductor memories can be prevented from being degraded. Additionally, since the variations in voltage of the bit lines are enlarged, the data reading time can be shortened. <IMAGE>
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