FLOOR PLAN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a floor plan method capable of exactly estimating wiring length and wiring congestion degree. SOLUTION: By designating the position of a block in a region unit in which a chip flat surface is divided into grid shapes and arranging a logic element virtually generated in the divided unit region, the wiring length and the wiring congestion degree are accurately estimated. COPYRIGHT: (C)2003,JPO