| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic simulation device for semiconductor integrated circuit capable of performing a simulation with a high verification ratio by facilitating the preparation of test patterns rich in variation and facilitating the confirmation of a logic simulation result. SOLUTION: An input pattern and an output expected value for the simulation are expressed by a structural body constituted of a starting pointer, a data size, a next pointer and a parameter of control information on a memory 104 within a test bench 102. A test scenario describing an arbitrary parameter is imparted to the test bench 102, the input pattern and the output expected value are automatically generated within the test bench 102, and they are stored in the memory 104 within the test bench 102. The input pattern is imparted to the semiconductor integrated circuit 112 from the test bench 102, and an output from the semiconductor integrated circuit 112 and the output expected value automatically prepared within the test bench 102 are compared. COPYRIGHT: (C)2003,JPO
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