| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To increase processing speed by reducing a surplus waiting time at boosting operation and drop operation of internal voltage with sufficient pulse width secured in order to uniformly keep a data write characteristic for a memory cell and a data erasing characteristic of a memory cell. <P>SOLUTION: When writing and erasing of data for a memory cell are performed, a processing circuit 1 switches an internal clock signal generated by an internal clock generating circuit 3 so that at controlling operation of boosting and dropping internal voltage, a clock period is made a short clock period corresponding to a voltage characteristic of a boosting and dropping circuit, and at controlling operation of applying write and erasure pulse voltage for a memory cell, a clock period is made a long clock period being suitable for write and erasure. <P>COPYRIGHT: (C)2003,JPO</p> |
