发明名称 SCRAMBLER AND DESCRAMBLER
摘要 PROBLEM TO BE SOLVED: To provide a scrambler and a descrambler capable of bypassing data. SOLUTION: When bypassing, resistors 12-1 to 12-m are reset, all outputs of exclusive OR gates 10-2 to 10-m become low level and an incoming data is output from an exclusive OR gates 10-1 as it is. Consequently, a scrambler can confirm whether the data before scramble processing is correct or not. When bypassing, resistors 14-1 to 14-m are reset, all outputs of exclusive OR gates 16-2 to 16-m become low level and the data scrambled from an exclusive OR gate 16-1 is output as it is. Consequently, a descrambler can confirm what kinds of errors occurs from a transmission line to the descrambler. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003244132(A) 申请公布日期 2003.08.29
申请号 JP20020040097 申请日期 2002.02.18
申请人 MITSUBISHI ELECTRIC CORP 发明人 ISHIWAKI MASAHIKO
分类号 G09C1/00;H04L9/08;H04L9/22;H04L25/03;(IPC1-7):H04L9/22 主分类号 G09C1/00
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