Method and apparatus for implementing a selectively operable clock booster for DDR memory or other logic modules which utilize partially-defective memory parts, or a combination of partially-defective and flawless memory parts

摘要

A method and apparatus for implementing a selectively operable clock booster for DDR memory and other logic modules, which utilize partially-defective memory parts or a combination of partially-defective and flawless memory parts. The method and apparatus include an improved clocking method and system, which enables the use of partially-defective memory parts without distorting the clock signal. In one embodiment, a Phase-Locked Loop circuit and a clock patching network are used to significantly reduce clock distortion on a memory module.