| 摘要 |
A reprogrammable architecture for an arbiter (100) is described. The arbiter (100) is designed to be fair, fast, and simple to implement in circuitry, particularly in programmable logic. In embodiments, the arbiter (100) arbitrates amongst n-many requesters, labeled Requester 0, Requester1, …, Requester n-1. The arbiter (100) operates by multiplexing n-many connectors, which enables dynamic reprioritizing of the requests. Thus, n-many connectors, labeled Connector0 through Connectorn-1, are bijectively multiplexed to the n-many requesters. The requests from the connectors may then be reprioritized by altering the bijective map from the connectors to the requestors.
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