| 发明名称 |
Task-based hardware architecture for maximization of intellectual property reuse |
| 摘要 |
A task-based chip-level hardware architecture. The architecture includes a task manager for managing a task with task information, and a task module operatively connected to the task manager for performing the task in accordance with the task information.
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| 申请公布号 |
US2003163507(A1) |
申请公布日期 |
2003.08.28 |
| 申请号 |
US20020083042 |
申请日期 |
2002.02.26 |
| 申请人 |
ZARLINK SEMICONDUCTOR V.N. INC. |
发明人 |
CHANG RONG-FENG;BARRACK CRAIG I.;WANG LINGHSIAO |
| 分类号 |
G06F9/00;G06F9/40;G06F9/46;G06F9/50;G06F17/50;(IPC1-7):G06F9/00 |
主分类号 |
G06F9/00 |
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