发明名称 Speed data processing system and method
摘要 A backplane of a data processing system is configured to include a current boost circuit for each net. The boost circuit is coupled to a common point for the net and is triggered to provide a boost current in response to a detected change in a signal on the net. The boost circuit has the capacity to provide a considerably larger drive current than does the conventional driver on the circuit board connected to the backplane. Thus when a conventional driver starts to drive a signal on the net from one logic state to the other, the boost circuit detects the initiation of change and supplies a boost current to cause a rapid change in logic state. Preferably each terminal on the net is coupled to the common point by a trace which includes both a highly conductive portion and a portion including a damping impedance. The damping impedance is chosen to approximate the characteristic impedance of the trace coupling the terminal to the common point and the associated loading of that trace.
申请公布号 US2003160635(A1) 申请公布日期 2003.08.28
申请号 US20030349314 申请日期 2003.01.21
申请人 ARIZONA DIGITAL, INC. 发明人 BERDING ANDREW R.
分类号 G06F13/40;(IPC1-7):H03K19/00 主分类号 G06F13/40
代理机构 代理人
主权项
地址