| 摘要 |
In order to effectively explore a binary decision diagram for synthesizing a logic circuit, a tentative circuit comprised of AND gates and OR gates is synthesized from a logic function. The number of gates in this circuit to which two input variables are simultaneously associated are counted and used as correlation between the two input variables. A correlation matrix for correlation among all of the input variables is generated. The input variables are sequentially grouped from a set of input variables with strongest correlation in the correlation matrix: These groups are registered into a correlation tree, and an intergroup correlation tree is produced. These groups are sequentially selected from a group with the least correlation, and the intragroup order of the selected group is changed from one to another. A binary decision diagram is explored which satisfies the most appropriate condition in that group (such as the minimum number of nodes, the minimum delay, and the minimum area). The above processes repeated for all groups. Each node of the binary decision diagram thus obtained is substituted by a selector and each selector circuit is substituted by a circuit of a transistor level.
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