| 摘要 |
An image display circuitry comprises frame buffers 32 - 34 for storing image data DTAW, DTRW and logical combining data DTCW respectively, and a combining circuit 46. Data buses and address buses of the frame buffers 32 and 34 are time-sharingly controllable from an MPU independently of those of the frame buffer 33. Each frame of the image data DTRW is synchronized with a vertical synchronizing signal, and stored to the frame buffer 33. Each frame of the image data DTAW and the logical combining data DTCW is separately and independently stored to the frame buffers 32 and 34 by the MPU within a storage period of a corresponding frame of the image data DTRW. The combining circuit 46 combines image data DTAR and DTBR pixel by pixel on the basis of logical combining data DTCR within a specified period during a vertical retrace period. <IMAGE>
|
