发明名称 APPARATUS FOR TESTER SIMULATION AND METHOD FOR TESTER SIMULATION
摘要 <P>PROBLEM TO BE SOLVED: To actualize an apparatus for tester simulation allowing the same test program as one of an actual machine to run thereon and a method for tester simulation. <P>SOLUTION: This is an improvement over a tester simulation apparatus used for simulating a test for a tested object by using a tester. This apparatus is characterized by having a DUT (device under test) simulation means for simulating behaviors of the tested object, a tester simulation means for simulating behaviors of the tester based on a test program, and a delay simulation means for delaying behaviors of transferring signals, by a certain amount of delay, between the DUT simulation means and the tester simulation means. <P>COPYRIGHT: (C)2003,JPO
申请公布号 JP2003240824(A) 申请公布日期 2003.08.27
申请号 JP20020041035 申请日期 2002.02.19
申请人 YOKOGAWA ELECTRIC CORP 发明人 ANZAI SADASHIGE
分类号 G01R31/28;G01R31/3183;G06F11/22 主分类号 G01R31/28
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