| 摘要 |
A method and apparatus are disclosed for verifying the functional design of a system's response to propagation delays from the inputs of source synchronous links during testing. The system emulates propagation delays by receiving data slice from a source, applying a random or known delay to the data slice, and sending the delayed data slice to the chip under test. In one embodiment, multiple data slices having varying delay values may be used to test combinations of delays. A programmable delay.element is used to emulate the propagation delays. This is may be implemented at the hardware description level by receiving the data slice onto multiple data buses, applying a different delay to the data slice on each data bus, and sending the delayed data slices as inputs into a multiplexor. The multiplexor may have a selector input that determines which amount of delay to test. Alternatively, the delay may be emulated using a higher level programming language and creating a multidimensional array. In one dimension, the array receives different data slices, and in the other it assigns different delay values. The multidimensional array then receives multiple data slices at the same time. Each delay value is stored in a different array location, depending upon the delay assigned to the data slice. An output entry is sent to the chip under test. The array entries may be shifted each clock cycle to the output entry, or a pointer may be used to specify a different output entry each clock cycle.
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