发明名称
摘要 A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.
申请公布号 JP2003525470(A) 申请公布日期 2003.08.26
申请号 JP20010563954 申请日期 2001.02.26
申请人 发明人
分类号 G03F1/00;G03F1/36;G03F1/70;G06F17/50;H01L21/027 主分类号 G03F1/00
代理机构 代理人
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