| 摘要 |
A monolithic CMOS programmable digital intermediate frequency receiver includes a programmable memory, a clock generator, a sigma delta converter, a digital downconverter, and a decimation filter network. The programmable memory receives and stores a first value representative of a programmable parameter k and a second value representative of programmable parameter N. Coupled to the programmable memory, the clock generator generates a first clock signal, a second clock signal and a third clock signal. The first clock signal has a first frequency, fl, the second clock signal has a second frequency approximately equal to fl/k and the third clock signal has a third frequency approximately equal to fl/N. The sigma delta converter samples an analog input signal having an intermediate frequency using the first clock signal to generate a first set of digital signals. The digital downconverter mixes down the first set of digital signals using the second clock signal to generate a second set of digital signals. Finally, the decimation filter network filters the second set of digital signals using the third clock signal to generate a third set of digital signals.
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