| 摘要 |
<P>PROBLEM TO BE SOLVED: To simplify mapping of a logic verification objective circuit to a FPGA and wiring between FPGA, to avoid a delay of signal transmission due to a wiring delay, and to shorten a time required for deciding a wiring route in a logic verification method using the FPGA. <P>SOLUTION: A module FPGA 18-n and a switch FPGA 19 are mounted on a logic verifying board 17. In the module FPGA 18-n, a P/S conversion circuit 21-n and S/P conversion circuit 24-n are mapped in addition to the logic verification objective circuit 20-n, while in the switch FPGA 19, a transfer circuit capable of transferring one or two serial signals transferred from one or two module FPGA for the same transfer destination to the module FPGA in the same transfer destination is mapped. <P>COPYRIGHT: (C)2003,JPO |
