| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL (phase-locked loop) circuit capable of holding the responsiveness of the PLL circuit and effectively using the band of the oscillation frequency characteristics of a VCO (voltage controlled oscillator). <P>SOLUTION: Clock signals 2s inputted from the outside of a device and an output clock 10s outputted from the VCO 9 are compared. Corresponding to the compared result, in the adjustment of the VCO 9, a maximum current 13s outputted from a maximum current generation circuit 13 is controlled and supplied to a frequency control DAC 6 and maximum frequency control signals 141s supplied from a system controller 14 and selected by a selector 80 are digital/analog converted. Also, the maximum current 13s outputted by the maximum current generation circuit 13 is adjusted by a maximum current gain adjustment circuit 83 and supplied to a phase control DAC 7 and maximum phase control signals 142s selected by a selector 81 are digital/analog converted. <P>COPYRIGHT: (C)2003,JPO |
