| 摘要 |
PROBLEM TO BE SOLVED: To fabricate a high speed CMOS device having an SiGe layer subjected to strain relaxation with high efficiency. SOLUTION: On a silicon substrate 10, a strained SiGe layer 16 having germanium concentration of about 20%-40% and a silicon cap layer 18 are formed by epitaxial growth, and then a gate oxide layer and a first polysilicon layer 22 are grown on the silicon cap layer 18. Subsequently, H<SP>+</SP>ions are implanted down to a depth below the interface of the strained SiGe layer 16 and the silicon substrate 10 and a trench 26 reaching the inside of the silicon substrate 10 is made by STI. The resulting structure is annealed at about 700°C-900°C for about 5-60 min in order to relax the strained SiGe layer 16. Thereafter, an oxide layer 28 and a second polysilicon layer 30 are deposited on the resulting structure to fill the trench 26 and the surface is planarized in flush with the second polysilicon layer 30 in the trench 26. COPYRIGHT: (C)2003,JPO
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