| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic model creation method capable of performing logic simulation at the function level of the whole circuit including the standby state and operative state of a CMOS circuit for making MTCMOS or at the gate level without correcting the description of the CMOS circuit describing the function level specifications or gate level specifications during normal operation. SOLUTION: The MTCMOS circuit is grasped as a host hierarchical block of the CMOS circuit in the MTCMOS circuit, a digital circuit for performing logic verification is hierarchically divided into blocks and described, and in the specification description of the CMOS circuit in the MTCMOS circuit, the logic operation when a power supply interrupt transistor is in the on-state is described, and in the specification description of the MTCMOS circuit, included is the description to the effect that during the operation, a signal value of a signal line connected to an input pin is applied to the input pin, and during the standby operation, an undefined value is applied to the input pin. COPYRIGHT: (C)2003,JPO
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