| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress a frequency fluctuation and a phase fluctuation in generated clock signals even when noise is mixed in horizontal synchronizing signals, horizontal synchronizing pulses Ph are omitted and a phase change is generated in the horizontal synchronizing signals by a generation of skew or the like. <P>SOLUTION: A PLL circuit 22 is provided and a synchronization detection window circuit 24 for generating synchronization detection window signals on the basis of comparison signals is provided. The phase comparison period TD of the synchronization detection window signals is defined as a set period including the pulse width period of comparison pulses Pc, phase comparison in a period other than the phase comparison period TD is inhibited and the fluctuation due to noise mix-in and omission is suppressed. A skew detection window circuit 28 for detecting the skew generation and outputting reset signals to a frequency divider 32 is provided and a fluctuation in the clock signals at the time of the generation of skew is suppressed. <P>COPYRIGHT: (C)2003,JPO |
