| 摘要 |
In the synchronous DRAM controller of this invention, when receiving a read request to an SDRAM (Synchronous Dynamic Random Access Memory) from an internal bus, a control sequencer outputs a start readout signal that synchronizes with the system clock signal. A start readout operation unit, receiving the start readout signal from the control sequencer, starts transferring a readout clock signal to the SDRAM. A signal delay path receives the readout clock signal from the start readout operation unit, delays the signal to transfer it to the SDRAM, and further delays a part of the readout clock signal to transfer it to the control sequencer. A temporary read data retention unit receives and temporarily retains a read data outputted from the SDRAM at each cycle of the readout clock signal through the signal delay path. The control sequencer sends a read data storage enabling signal to the temporary read data retention unit, when receiving a part of the readout clock signal from the signal delay path, makes the temporary read data retention unit temporarily store the read data taken in to be synchronized with the readout clock signal, and at the same time outputs a read data readout enabling signal to the temporary read data retention unit so as to output the read data in synchronization with the system clock signal.
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