| 摘要 |
A semiconductor device which has complementary logic gates, including: a field effect transistor 101 having a first conductivity type channel, a first conductivity type well region 202 formed on a semiconductor substrate 102, a second conductivity type channel layer 203 formed on the surface of the region 202, a first wire 112 that connects an end 204 of the second conductivity type channel layer 203 to a first conductivity type drain region 106, a second wire 208 that connects the other end 205 of the second conductivity type channel layer 203, and a third wire 208 that connects the first conductivity type well region 202 to a second power source that has the same polarity as a first power source; and manufacturing method thereof. This semiconductor device and manufacturing method enables low power consumption and simple control of threshold voltage values as well as avoiding increases in the number of manufacturing processes.
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