| 摘要 |
Methods and systems for protecting integrated circuits ("ICs") from power-on sequence currents, including methods and systems for biasing transistors in paths susceptible to power-on sequence damage such that these paths do not have substantial current flow unless the power supplies controlling the gate of the susceptible transistors are powered on. In an embodiment, the invention is applied to a circuit having a first and second IC terminals coupled to a first and second power supplies, respectively. The invention protects the circuit in the event that the first power supply is powered-on before the second power supply is powered-on. The method includes sensing voltage amplitudes from the first and second power supplies. When first power supply is powered-on before the second power supply is powered-on, the first IC terminal is coupled to the second IC terminal. The substantially prevents undesired power-on sequence currents from flowing between the first and second IC terminals. For example, in an embodiment, the circuit to be protected is a transistor, such as a PMOS or an NMOS transistor. The first and second IC terminals are coupled to a source and a gate of the transistor. When the source and gate are coupled together, there is little or no voltage across the source/gate junction. As a result, little or no power-on sequence current flows through the source/gate junction. When the second power supply is powered-on, the first and second IC terminals are de-coupled and the circuit is allowed to operate normally. In an embodiment, the first and second IC terminals are also de-coupled when the first power supply is off.
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