发明名称 Electronic circuit package
摘要 An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.
申请公布号 US2003156441(A1) 申请公布日期 2003.08.21
申请号 US20030370518 申请日期 2003.02.24
申请人 KANEKAWA NOBUYASU;IHARA HIROKAZU;AKIYAMA MASATSUGU;KAWABATA KIYOSHI;YAMANAKA HISAYOSHI;OKISHIMA TETSUYA 发明人 KANEKAWA NOBUYASU;IHARA HIROKAZU;AKIYAMA MASATSUGU;KAWABATA KIYOSHI;YAMANAKA HISAYOSHI;OKISHIMA TETSUYA
分类号 G06F1/18;G06F3/00;G06F11/10;G06F11/22;G06F12/16;G06F15/78;G11C5/00;H01L23/495;H01L23/50;H01L23/538;H01L25/04;H01L25/065;H01L25/18;(IPC1-7):G11C5/02 主分类号 G06F1/18
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