SEMICONDUCTOR FABRICATION PROCESS, LATERAL PNP TRANSISTOR, AND INTEGRATED CIRCUIT

摘要

A method in the fabrication of an integrated bipolar circuit including a lateral PNP transistor comprises the steps of: providing a p-type doped substrate (10, 41) having an upper surface; forming in the substrate (10, 41) a buried n+-type doped region (31) for a PMOS transistor structure; forming in the substrate (10, 41) an n-type doped region (41) above the buried n+-type doped region (31); forming field isolation areas (81) around, in a horizontal plane, the n-type doped region (41); forming a PMOS gate region (111, 194) on the n-type doped region (41); forming a diffused n>+<-type doped contact from the upper surface of the substrate (10, 41) to the buried n>+<-type doped region (31); the contact being separated from, in a horizontal plane, the n-type doped region (41); forming a p-type doped polysilicon source region (151') on the n-type doped region (41); forming a p-type doped source (198) region in the n-type doped region (41) by means of diffusion from the p-type doped polysilicon source region (151'); forming a p-type doped drain (199) region in the n-type doped region (41); and connecting the PMOS transistor structure to operate as a PNP transistor, wherein the source region (198) is connected to the gate region (194) and constitutes an emitter of the PNP transistor; the drain region constitutes a collector of the PNP transistor; and the n-type doped region (41) constitutes a base of the PNP transistor.