发明名称 |
Design method of a logic circuit |
摘要 |
Even if only logic circuits described in HDL are distributed over a network, if the logic synthesis ability is insufficient, the overall design capability cannot be enhanced; e.g., a sufficient performance of a gate level logic circuit cannot be attained, or it takes a long time to complete logic synthesis. Considering design skills for logic synthesis are considered as property, the invention enables distribution of design skills between a plurality of design sites over a network interconnecting computers. Charges for a design skill are set for the rates of improvement to the performance of the logic circuit that was refined by the design skill. Desired circuit performance can be attained in a shorter period by shortening the design phases in which an RTL logic circuit is supplied as input and by logic synthesis thereon, a gate level logic circuit is output.
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申请公布号 |
US6609244(B2) |
申请公布日期 |
2003.08.19 |
申请号 |
US20010931879 |
申请日期 |
2001.08.20 |
申请人 |
HITACHI, LTD.;HITACHI ULSI SYSTEMS CO., LTD. |
发明人 |
KATO NAOKI;YANO KAZUO;CHIKATA HIDETOSHI;YAMASHITA SHUNZO |
分类号 |
G06F17/50;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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