发明名称 |
Apparatus and method for a memory storage cell leakage cancellation scheme |
摘要 |
An apparatus is described having a plurality of storage cells coupled between a first bit line and a second bit line. The apparatus also has a first transistor that pre-charges the first bit line and provides a first supply of current for one or more leakage currents drawn from the first bit line by any of the plurality of storage cells. The apparatus also has a second transistor that pre-charges the second bit line and provides a second supply of current for one or more leakage currents drawn from the second bit line by any of the plurality of storage cells.
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申请公布号 |
US6608786(B2) |
申请公布日期 |
2003.08.19 |
申请号 |
US20010823575 |
申请日期 |
2001.03.30 |
申请人 |
INTEL CORPORATION |
发明人 |
SOMASEKHAR DINESH;YE YIBIN;HAMZAOGLU FATIH;DE VIVEK K. |
分类号 |
G11C7/12;(IPC1-7):G11C7/00;G11C7/02;G11C8/00 |
主分类号 |
G11C7/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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