发明名称 Layout architecture to optimize path delays
摘要 An apparatus comprising a first stage and a second stage. The first stage may comprise a first section and a second section. The second stage may be embedded between the first and second sections. The first and second stages may be configured to equalize signal paths between a plurality of inputs of the first stage and a plurality of outputs of the second stage.
申请公布号 US6609243(B1) 申请公布日期 2003.08.19
申请号 US20010941352 申请日期 2001.08.29
申请人 CYPRESS SEMICONDUCTOR CORP. 发明人 EVANS BRIAN P.;HUNT JEFFERY SCOTT
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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