发明名称 |
Enhanced ZDB feedback methodology utilizing binary weighted techniques |
摘要 |
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a plurality of output clock signals in response to a reference clock signal and a feedback signal. The second circuit may be configured to select one of the plurality of output clock signals as the feedback signal in response to a first control signal. The first control signal may be configured to minimize a difference in delay between the plurality of output clock signals.
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申请公布号 |
US6608530(B1) |
申请公布日期 |
2003.08.19 |
申请号 |
US20010017709 |
申请日期 |
2001.12.14 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
GREEN DAVID;KATAGIRI DAIGO |
分类号 |
G06F1/10;H03L7/08;H03L7/18;(IPC1-7):H03L7/07 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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