Method of control cell placement to minimize connection length and cell delay

摘要

A method of control cell placement for an integrated circuit design includes the steps of receiving as input a description of a datapath structure for a hardmac; calculating a globally optimum placement with respect to connection length and delay for a group of control cells in the plurality of control cells; placing the plurality of control cells in at least one placement box; adding the placement of the plurality of control cells to an existing placement of a plurality of datapath cells in the description of the datapath structure to generate a globally optimum datapath structure for the plurality of control cells; and generating as output the globally optimum datapath structure.