发明名称 PROGRAM VERIFICATION SYSTEM
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a programming verification system which programs fairy a defective bit again without applying stress excessively to bit logic in a device. <P>SOLUTION: This system detects a bit failing in programming verifying operation, programs the bit again utilizing adjusted programming voltage, obtains desired Vt, reduces stress for the bit, and achieves narrow Vt distribution. <P>COPYRIGHT: (C)2003,JPO</p>
申请公布号 JP2003228985(A) 申请公布日期 2003.08.15
申请号 JP20020297726 申请日期 2002.10.10
申请人 FUJITSU LTD 发明人 YANO MASARU
分类号 G01R31/28;G11C16/02;G11C16/04;G11C16/06;G11C16/34;(IPC1-7):G11C16/02 主分类号 G01R31/28
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