| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a low-cost and high-performance PLL circuit capable of storing an optimum frequency oscillation voltage which will not deteriorate the responsiveness or jitter performance, even using a low-speed AD converter. <P>SOLUTION: An input voltage of a voltage controlled oscillator 4 is inputted to of an AD converter 17. In an initial operation, a switch 13 is set to pass a signal from a phase comparator 2 to a low-pass filter 3 and a switch 11 is set to cut off a signal from a D/A converter 9 to the low-pass filter 3, so that only the voltage control oscillator 4, a frequency divider 5, the phase comparator 2, and the low-pass filter 3 form a loop. After the PLL circuit goes into a lock state, they are set to cut off the signal from the comparator 2 to the filter 3 and pass the signal from the D/A converter 9 to the filter 3 to feed the oscillator 4 with an optimum frequency oscillation voltage stored in a latch circuit 8 as a digital value. <P>COPYRIGHT: (C)2003,JPO |
