| 摘要 |
PROBLEM TO BE SOLVED: To capture write data appropriately into a DRAM device even if a command delay exceeds the domain of a reference clock. SOLUTION: The DRAM device 40, when receiving a write command from a memory controller 20 via an external C/A bus 106, a regulator 50 and an internal C/A bus 60, stands by for a write flag, and next when receiving a write flag from the memory controller 20 via a write flag signal line 100, starts to count to a given clock number at a count starting point by the write flag. The DRAM device 40 then captures write data propagated through a DQ bus 104 at a write data capture starting point when the given clock number passes. COPYRIGHT: (C)2003,JPO
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