| 摘要 |
PROBLEM TO BE SOLVED: To enable formation of a membrane with high yield without decreasing an etching rate in the case of etching formation of a cavity, when a desired etching hole cannot be formed in a semiconductor device having a membrane. SOLUTION: This manufacturing method is provided with a process for forming a p-type layer 12 having a prescribed thickness on one surface 11 of an n-type silicon substrate 10, a process for forming the membrane 20 on the p-type layer 12, a process for forming an etching hole 27 at a part position corresponding to the cavity 13 in the membrane 20, and a process for forming the cavity 13 by injecting etching solution 31 via the etching hole 27, etching the p-type layer 12, and eliminating it in the state that an inverse voltage is applied to an pn junction between the n-type silicon substrate 10 and the p-type layer 12. COPYRIGHT: (C)2003,JPO
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