| 摘要 |
PROBLEM TO BE SOLVED: To provide an evaluation test method of semiconductor element using a simulated wiring pattern which may be accurately evaluated. SOLUTION: A linear portion S, a pair of parallel wirings 12a, 12b combining dog-leg shape L, and measuring pads 12A,12B connected to one end of these wirings, are formed on an insulation film 11 formed on the surface of a semiconductor wafer. Width and interval of these patterns of wirings 12a, 12b are set identical to the width and interval of the actual IC patterns simultaneously formed on the semiconductor wafer or set smaller than the sizes of these patterns. After formation of the patterns, the continuity condition of the pads 12A, 12B is measured to test the short-circuit among the patterns. Particularly, the dog-leg shape L easily generates short-circuit due to irregular growth of pattern. Accordingly, accurate evaluation test can be realized with the simulated wiring pattern including the dog-leg shape L. COPYRIGHT: (C)2003,JPO
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