发明名称 DETECTION CIRCUIT OF CLOCK ABNORMALITY ON MULTIPLE WIRINGS
摘要 <p><P>PROBLEM TO BE SOLVED: To quickly detect adverse effects on a waveform due to reflection or noises, when they are caused in an input waveform of an arbitrary buffer on multiple wiring in a clock distribution arrangement to a plurality of LSIs mounted in a package. <P>SOLUTION: An updown counter 2 begins from an initial value O, and 1 is added thereto by a clock of an updown counter input 21 from a buffer 4, and 1 is subtracted therefrom by a clock of an updown counter input 22 from a buffer 5. Also, the calculated value of the counter is output to an alarm-issuing unit 3. The alarm-issuing unit 3 monitors the value of the counter inputted from the updown counter 2, and outputs an alarm, when an abnormal value is detected. <P>COPYRIGHT: (C)2003,JPO</p>
申请公布号 JP2003228436(A) 申请公布日期 2003.08.15
申请号 JP20020026312 申请日期 2002.02.04
申请人 NEF:KK 发明人 TAMAI HIDEAKI
分类号 G06F1/04;G06F1/10;(IPC1-7):G06F1/04 主分类号 G06F1/04
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