发明名称 ADIABATIC DYNAMIC LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To clarify the relation between a load connected to an output terminal of an adiabatic dynamic logic (ADCL) circuit and an output hold capacitance, and to provide a stable operative ADCL circuit. SOLUTION: The values of an output hold capacitance, corresponding to voltage ranges (here 0.95 V or lower and 3.15 V or higher) are obtained. From Fig. 4 (a), an output hold capacitance of 0.12 pF or higher is needed for an output voltage Vout of 0.95 V or lower. In Fig. 4 (b), an output hold capacitance of 0.0675 pF or more is needed for an output voltage Vout of 3.15 V or higher. Hence, for a stable operation of the ADCL circuit, an output hold capacitance needs to be 0.12 pF or higher. This value is approximately ten times an input capacitance of a load, 0.0127 pF, connected to an output terminal of the ADCL circuit used for calculation. COPYRIGHT: (C)2003,JPO
申请公布号 JP2003229759(A) 申请公布日期 2003.08.15
申请号 JP20020028706 申请日期 2002.02.05
申请人 TOKYO CATHODE LABORATORY CO LTD 发明人 TAKAHASHI KAZUKIYO
分类号 H01L27/04;H01L21/822;H03K19/0948;(IPC1-7):H03K19/094 主分类号 H01L27/04
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