发明名称 LOGICAL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a logical circuit which can execute FA command in a relatively simple configuration. <P>SOLUTION: A delta register 4 is prepared at the output side of an accumulator 3. First, data in FA queue 1 is transmitted to FA register 2. Next, a synchronous variable (semaphore) stored in a memory 6 and a value in the FA register 2 are transmitted to the accumulator 3. This operation is conducted only at the first time. And, an output of the accumulator 3 is stored in the delta register 4. Then, the second data in the FA queue 1 is transmitted to the accumulator 3. Meanwhile, data in the delta register 4 is also transmitted to the accumulator 3. Next, an output of the accumulator 3 is stored in the delta register 4. Furthermore, the same process is conducted for the data of the third and the further in the FA queue 1. When the FA queue 1 is empty or the data in the FA queue 1 accesses a different address from what it used be, the data in the delta register 4 is written back to the memory 6 as the synchronous variable. <P>COPYRIGHT: (C)2003,JPO
申请公布号 JP2003228482(A) 申请公布日期 2003.08.15
申请号 JP20020026663 申请日期 2002.02.04
申请人 NAKAYAMA TAIICHI 发明人 NAKAYAMA TAIICHI;KAWAMI TATSUYA
分类号 G06F9/34;G06F9/30;G06F12/00 主分类号 G06F9/34
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