Schaltung mit gemischten Signalen und Geräte integrierter Schaltungen

摘要

In mixed-signal circuitry signal control circuitry (12) is interposed between digital circuitry (10) and analog circuitry (14). The signal control circuitry comprises a plurality of individual clocked signals (L1-Ln), each connected for receiving one or more first digital signals (T1-Tn) and also connected for receiving a clock signal (CLK) . Each clocked circuit derives from the received first digital signal(s) at least one second digital signal (TCK1-TCKn) and applies that derived second digital signal to an analog-circuitry input at a time determined by the received clock signal. The signal control circuitry also comprises clock distribution circuitry including a plurality of block buffer circuits (B1-Bn) connected in common for receiving a basic timing signal (BCLK). Each clock buffer circuit derives from the basic timing signal such a clock signal (CLK1-CLKn) for application to one or more corresponding ones of the said clocked circuits (L1-Ln).