发明名称 |
Apparatus and method for improved execution of a software pipeline loop procedure in a digital signal processor |
摘要 |
A program memory controller unit includes apparatus for the execution of a software pipeline procedure in response to a predetermined instruction. The apparatus provides a prolog state, a kernel state, and an epilog state for the execution of the software pipeline procedure. In addition, in response to a predetermined condition, the software pipeline loop procedure can be terminated early. Apparatus is provided whereby a second software pipeline loop procedure can be initiated prior to the completion of a first software pipeline procedure. Two additional instructions are provided for addressing problems resulting from hardware pipeline delays and for more efficient program execution.
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申请公布号 |
US2003154469(A1) |
申请公布日期 |
2003.08.14 |
申请号 |
US20020225036 |
申请日期 |
2002.08.21 |
申请人 |
ANDERSON TIMOTHY;ASAL MICHAEL D.;STOTZER ERIC J. |
发明人 |
ANDERSON TIMOTHY;ASAL MICHAEL D.;STOTZER ERIC J. |
分类号 |
G06F9/32;G06F9/38;G06F9/45;G06F15/00;(IPC1-7):G06F9/45 |
主分类号 |
G06F9/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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