| 摘要 |
PURPOSE: A method for fabricating a gate including a salicide layer of a semiconductor device is provided to satisfy the critical dimension and the vertical etch profile that are essential to a high integrated device having a line width of a gate less than 0.18 micrometer by using an oxide layer for a hard mask. CONSTITUTION: An active region and a field region are defined in a semiconductor substrate(100). An isolation layer(101) is formed in the field region of the substrate. After a gate insulation layer(102) and a conductive layer are deposited on the resultant structure, the hard mask is selectively formed on the conductive layer. The conductive layer is selectively etched to define a gate electrode(103a) by using the hard mask. A spacer(106a) is formed on the sidewall of the gate electrode while the hard mask is selectively removed through an over-etch process. A salicide layer(107) is formed on the gate electrode and the active region.
|
