发明名称 |
Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support |
摘要 |
A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, processing the input to render an arithmetic result. If the processor is in a second mode, performing a token specific operation. And producing an output. The present invention also provides a processor comprising a first instruction set engine, a second instruction set engine, and a mode identifier. A plurality of floating-point registers are shared by the first instruction set engine and the second instruction set engine. A floating-point unit is coupled to the floating-point registers. The floating-point unit processes an input responsive to the mode identifier and the input to produce an output.
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申请公布号 |
US2003154366(A1) |
申请公布日期 |
2003.08.14 |
申请号 |
US20000505949 |
申请日期 |
2000.02.15 |
申请人 |
CHOW MICHAEL;GANESAN ELANGO;PHILLIPS JOHN WILLIAM;ZAIDI NAZAR ABBAS |
发明人 |
CHOW MICHAEL;GANESAN ELANGO;PHILLIPS JOHN WILLIAM;ZAIDI NAZAR ABBAS |
分类号 |
G06F9/00;G06F9/302;G06F9/318;(IPC1-7):G06F9/00 |
主分类号 |
G06F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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