DIGITAL PHASE LOCKED LOOP

摘要

The invention relates to a digital phase locked loop (PLL) 12 for demodulating an intermediate frequency signal. The digital phase locked loop12 comprises two coordinate rotation digital computers 24 and 30 in its phase detector. The robustness of the PLL 12 can be improved by means of a gain control circuit 27, a sign detector 20, a carrier monitoring circuit 28 and an adjustable loop filter 32.