发明名称 CLOCK SIGNAL GENERATION CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR GENERATING CLOCK SIGNAL
摘要 PURPOSE: A clock signal generation circuit for semiconductor memory device and a method for generating a clock signal are provided to prevent the power consumption due to malfunctions by applying a read clock signal and a write clock signal to different circuit blocks, respectively. CONSTITUTION: A clock signal generation circuit for semiconductor memory device includes a plurality of internal clock signal generation portions(30,50), a read clock signal generation portion(80), and a write clock signal generation portion(90). The internal clock signal generation portions buffer external clock signals and generate internal clock signals. The read clock signal generation portion receives the internal clock signals and generate read clock signals when a read command is performed. The write clock signal generation portion receive the internal clock signals and generate write clock signals when a write command is performed.
申请公布号 KR20030067160(A) 申请公布日期 2003.08.14
申请号 KR20020007034 申请日期 2002.02.07
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM, JAE HUN;LEE, JONG WON;SEO, YEONG HUN
分类号 G11C7/22;(IPC1-7):G11C7/22 主分类号 G11C7/22
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